Integrated circuit designs have numerous active devices such as transistors laid out on a common substrate, typically silicon. In order to prevent electrical interference between the active devices, they are separated by isolation regions. Such isolation regions may be formed early in the fabrication process by masking the active regions and growing an insulator such as oxide in the nonmasked isolation regions. The grown oxide, referred to as field oxide, serves both to isolate and define the active regions. The active devices are formed by various processing steps and then covered with an insulator. In order to interconnect the various active devices, one or more overlying metalization layers are formed on top of the insulator with connections to the devices provided by openings in the insulator.
The development of integrated circuits has been characterized by the ever increasing number of devices placed on a single semiconductor substrate. In order to achieve higher device density, smaller geometry devices have been developed. One limitation to device dimensions is the minimum contact area or "footprint" required between metalization layers and active devices. In order to overcome this limitation, interconnections between adjacent active devices may be disposed underneath the insulating layer. Such interconnections, known as "local interconnects," are formed on top of the isolating field oxide and prior to the formation of overlying insulating and metalization layers.
A local interconnect formed between two active regions will typically connect a source/drain region of one active region to the source/drain region of the other. However, local interconnects may also be formed between polysilicon gate regions and between a polysilicon gate region and source/drain region. In general, local interconnects are used to connect electrodes of active devices.
Local interconnects do not eliminate the need for metalization layers. However, they do reduce some of the complexity of the metalization layers. In addition, the connection between a metalization layer and active device may be made by connecting the metalization layer to the local interconnect. Since the local interconnect may overlay the field oxide region, a relatively large area is available for the required connection. This permits the active device dimensions to be reduced.
Local interconnects are not generally made of the same metal as the metalization layers. The integrated circuit is subjected to relatively high temperatures during the formation of active devices. As these temperatures are sufficient to degrade typical metalization elements, a more stable conductor such as titanium silicide is typically used.
One process for producing local interconnect involves heating a layered strip of titanium and silicon to form a strip of titanium silicide. The heating also produces a layer of titanium nitride on the sidewalls of the titanium silicide strip which must be selectively removed. The titanium silicide is then subjected to a high temperature annealing. A problem with this process is that during the sidewall formation of titanium nitride some of the titanium in the layered strip is consumed. Thus, when the titanium nitride is removed the sidewalls are undercut. The degree of undercut is difficult to control, and the resulting local interconnect has a variable cross sectional area. Thus, the electrical resistance of the local interconnect, which is proportional to the cross sectional area, is unpredictable. In addition, the undercut can create voids when the insulating oxide is applied. Such voids can result in reliability problems, such as stress fractures.